This section is intended to provide information relevant to understanding the various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits can be designed as memory. Due to the downward scaling of transistors in modern circuitry, the geometric scaling of metal routing can increase back-end wire RC load (i.e., resistor-capacitor load), which can degrade memory operation speed (i.e., static random access memory operation speed). For instance, since transistor geometry is being scaled down, metal geometry is also scaled down. As such, resistance (R) of metal geometry and related capacitance (C) can become a significant problem with advanced nodes, so developing a bitline differential for a higher number of rows can be challenging. These challenging issues can adversely impact the timing and precharging of large RC of the bitline. These challenging issues can impact cycle time and power.